1. Field of the Invention
This invention relates to a method for measuring the kink effect of a transistor, particularly relates to a method for measuring the kink effect with an index representing to what extent the kink effect influence the transistor.
2. Description of the Prior Art
As the dimension of the semiconductor device is shrunk, the shallow trench isolation (STI) is usually used in isolation structure. As shown in FIG. 1, if there is an electrical field 10 crowding at the channel near the STI-active edge, and a voltage is applied to the channel by the gate poly 11. The corner electrical field 10a is larger than the channel center electrical field 10b. So the channel at the corner is formed before the whole channel enter the strong inversion state. In other words, a parasitic device is formed before the gate voltage reaches the threshold voltage. Thus even the transistor is at the off state, the channel is still formed by the parasitic device, and the off current (standby current: I.sub.off) is thus increased.
The profile of STI has a strong relationship with the kink effect of the transistor. The condition that increasing the kink effect is described as the following: the decrease of the radius r of birds beak, the decrease of the side wall angle .THETA., and the decrease of the terren height h. The change of the aforementioned factor result in the semiconductor device enter a weak inversion state. Especially, the increase of the standby current has a serious influence in the power assumption of the semiconductor device.
As usually used, the change of the logarithm of drain current versus gate voltage (log(I.sub.ds) versus V.sub.g) is a traditional method to observe how the semiconductor device is influenced by the kink effect. As shown in FIG. 2A, the drain current versus gate voltage curve (Ids-Vg curve) of a kink effect free device with various substrate bias is smooth. When the substrate bias is 0 volt, the Ids-Vg curve is curve 200, whereas, when the substrate bias is 1 volt, the I.sub.ds -V.sub.g curve is curve 201. The x-axis represents the gate voltage (V.sub.g) of the semiconductor device, and the y-axis represents the logarithm of the drain current (log(Ids)). When the I.sub.ds -V.sub.g curve of a device with kink effect is plotted, the result is shown in FIG. 2B. When the substrate bias is 0 volt, the I.sub.ds -V.sub.g curve is curve 210, whereas, when the substrate bias is 1 volt, the Ids-Vg curve is curve 211. It is obvious that when the semiconductor device with kink effect is utilized, there is some torsion in the Ids-Vg curves.
When the first order partial derivative of the Ids-Vg curve to gate voltage (V.sub.g) is taken, the drawing is shown in FIG. 3A. At this occurrence, the semiconductor device is kink effect free and the substrate bias is 2 volt. The curve 230 represents the logarithm value of the drain current (log(Ids)) and the curve 231 represents the transconductance (gm) of the semiconductor device when the substrate bias is 2 volt. As shown in FIG. 3B, the curve 240 represents the logarithm value of the drain current (log(Ids)) when the semiconductor device has the kink effect and the substrate bias is 2 volt. The curve 241 represents the transconductance (gm) of the semiconductor device when the substrate bias is 2 volt. It is obvious that, at some gate voltages, the transconductance has local maximum and local minimum.
When the second order partial derivative of the Ids-Vg curve to gate voltage (Vg) is taken; the plot is shown in FIG. 4A. At this occurrence, the semiconductor device is kink effect free and the substrate bias is 2 volt. The curve 250 represents the logarithm value of the drain current (log(Ids)) and the curve 251 represents the transconductance (gm) of the semiconductor device when the substrate bias is 2 volt. As shown in FIG. 4B, the curve 260 represents the logarithm value of the drain current (log(Ids)) when the semiconductor device has the kink effect and the substrate bias is 2 volt. The curve 261 represents the transconductance (gm) of the semiconductor device when the substrate bias is 2 volt. It is obvious that, at point A and point B, the transconductance has local minimum. At point C and point D, the transconductance has local maximum.
When the parasitic device enter the threshold state, the second order partial derivative of the Ids-Vg curve has the local minimum at the point A. When the channel of the semiconductor device enter threshold state, the second order partial derivative of the Ids-Vg curve has the local minimum at the point B. The point D stands for the occurrence that the channel of the semiconductor device enter the weak inversion. The point C represents the occurrence that the kink effect has the most serious influence. The point C and the point D both represent the start point of the change of increment of the channel current or the transconductance. So the point A and the point B represent the beginning and the end of the operation of the parasitic device respectively.
Observing the difference of gate voltage between the point A and point B, if the kink effect exists, then the difference of gate voltage between the point A and point B exists. Thus the traditional technology uses the difference of gate voltage between the point A and point B as an index. When the difference of gate voltage between the point A and point B exist, the kink effect exists in the semiconductor device. So the traditional technology use the maximum value of the second order partial derivative of the Ids-V.sub.g curve to represent the influence of the kink effect.
Because the unit of the expression of the foregoing representation is (log(A)V.sup.2), the increment of standby current resulted from kink effect and the static power assumption can not be described in the traditional technology. In addition, in the laboratory, the kink effect is measured by comparing the log(Id)-V.sub.g curve of a semiconductor device with kink effect and without kink effect. Whereas the aforementioned method can not be used in the wafer assurance testing (WAT) in mass production. Though a prior art ("ANALYSIS OF WIDTH EDGE EFFECT IN ADVANCED ISOLATION SCHEMES FOR DEEP SUBMICRON CMOS TECHNOLOGY" BY Psallagolity, M. Ada-HANIFI, M. Paoli, and Haond, IEEE Transactions on electron devices vol. 43, November 1996) indicates that the difference of the gate voltage when the parasitic channel enters the threshold and when the channel of the semiconductor device enter the strong inversion can be used as an index for the kink effect. Yet the method mentioned above can not describe the influence of the kink effect when the semiconductor device is at off mode.